74LS193 DATASHEET PDF

This circuit is a synchronous up down 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs. 74LS Synchronous 4-Bit Binary Counter with Dual Clock. General Description. The DM74LS circuit is a synchronous up/down 4-bit binary counter. The DM74LS circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by hav- ing all flip-flops clocked simultaneously.

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The direction of counting is determined by which. The output will change.

The counter is fully programmable; that is, each output may. View PDF for Mobile. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count down and count up inputs respectively of the succeeding counter.

A clear input has been provided which, when taken to a. The counters can then be easily cascaded by feeding the.

Datashset s Fully independent clear input s Synchronous operation s Cascading circuitry provided internally s Individual preset each flip-flop Ordering Code: The clear, count, and load. Similarly, the carry output produces a pulse equal in width.

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This feature allows the.

Synchronous 4-Bit Binary Counter With Dual Clock

Both borrow and carry outputs are available to cascade both the up and down counting functions. Both borrow and carry outputs. Fairchild Semiconductor Electronic Components Datasheet. This mode of operation eliminates the output counting spikes normally associated with asynchronous ripple- clock counters. These counters were designed to be cascaded without the. Synchronous operation is provided by hav- ing all datasehet clocked simultaneously, so that the outputs datasneet together when so instructed by the steering logic.

The direction of counting is determined by which count input is pulsed while the other count input is held HIGH. The borrow output produces a pulse equal in. These counters were designed to be cascaded without the need for 74l1s93 circuitry.

Similarly, the carry output produces a pulse equal in width to the count down input when an overflow condition exists. Synchronous operation is provided by hav. A 74ls1993 input has been provided which, when taken to a high level, forces all outputs to the low level; independent of the count and load inputs. The borrow output produces a pulse equal in width to the count down input when the counter underflows. This feature allows the counters to be used as modulo-N dividers by simply modi- fying the count length with the preset inputs.

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The clear, count, and load inputs are buffered to lower the drive requirements of clock drivers, etc. The output will change independently of the count pulses.

Motorola – datasheet pdf

The counter is fully programmable; that is, each output may be preset to either level by entering the desired data at the inputs while the load input is LOW. This mode of operation eliminates the output counting. The outputs of the four master-slave flip-flops are triggered.